1. Field of the Invention
The present invention relates generally to the field of data transmission, and specifically to circuitry for protecting hardware and critical data control circuits from the consequences of a data control failure, resulting from software or firmware failures. The present invention also relates to a data register robustness circuit.
2. Description of the Prior Art
In existing telecommunications transmission equipment, including digital multiplexers and fiber optic terminals, critical circuit control points provide data traffic path switching and control, all under the direction of software instructions, which may be stored in integrated circuit ROM and EPROM or other memories. In the event of a software control failure error condition, the potential for losing telecommunication traffic is great, hence it is a current practice in the telecommunications industry to duplicate much of the critical hardware, and to substitute spare circuitry for failed circuitry in the event of a hardware fault, thereby maintaining the traffic. Certain of the hardware control functions are directed by and are under the control of software as mentioned before, and errors in this software can cause the hardware to malfunction, since such hardware contains control points that are accessed by the software by simple read and write instructions. When the software fails so as to accidentally write to one or more control points, or to couple erroneous data to such control points, traffic can be lost.
The present invention provides a circuit which is interposed between the control points and the control software to detect the aforementioned erroneous control transmissions and to ensure that only accurate control data is coupled to the control points. In accordance with the present invention, a circuit is described which requires the control software to write the same data to a control point register twice in immediate sequence before the intended action can occur. Since the typical failure mode of control software is to start reading and writing random data to random locations, the present invention provides substantially improved robustness and protection against almost all normal software failures, since under such failure conditions, the same data would not be written to the same location two times in immediate sequence.
The known prior art includes various redundant signal processors which require duplication of hardware or complex and costly circuit arrangements, in contradistinction to the present invention. Examples of such prior art techniques are U.S. Pat. No. 3,883,891, titled redundant signal processing error reduction technique; U.S. Pat. No. 4,344,180 titled redundant word frame sunchronization circuit; U.S. Pat. No. 4,453,215 titled central processing apparatus for fault-tolerant computing; U.S. Pat. No. 3,800,286 titled address development techniques utilizing a content addressable memory; U.S. Pat. No. 4,130,241 titled control systems; and U.S. Pat. No. 4,456,997 titled facility for fail-safe data transmission between trackside equipment. None of the aforementioned prior art patents provide for the simplified technique of duplication of data and bit-by-bit comparison of the duplicated data in a robust register circuit, which overcomes the complexity and cost of the prior art, while protecting critical control points against software failures, as provided by the present invention.
It is therefore an object of the invention to provide a protective circuit and method to protect critical hardware control points in data transmission and in telecommunications equipment against software failures.
It is a further object of the invention to provide a robust register circuit and method for protection against loss of telecommunications traffic.
A further object of the invention is to provide a robust register circuit and method which requires that control data must be written twice in a row before it is recognized as valid data and coupled to a critical control point.